join us in upcoming EVEntS
Upcoming Workshops (Singapore)
Workshops for learning
For more details of the workshops, pls sent email to admin@launchxtec.com
Venue: Newcastle Australia Institute of Higher Education Singapore, 230 Victoria Street, #04-09/10, Bugis Junction Towers, S188024
Registration fee: SGD 800 per workshop (3 weeks before the workshop) and SGD 1,000 per workshop thereafter. We are pleased to offer the following discounts for block booking:
10% discount for registering for 3–5 workshops (any combination)
15% discount for registering for >6 workshops (any combination)
Please request a quotation by emailing admin@launchxtec.com or proceed with registration and payment via PayNow.
Beyond Moore's Law: Navigating the Advanced Semiconductor Packaging & Chiplet Revolution (25 -26 Jan 2027)
As traditional monolithic scaling hits its physical and economic limits, the semiconductor industry is undergoing a monumental paradigm shift. Advanced packaging is no longer just a protective housing for silicon—it has become the primary driver of system performance, energy efficiency, and cost optimization.
This comprehensive, technical masterclass provides a deep dive into the architectures, methodologies, and manufacturing innovations defining the post-Moore’s Law era. Attendees will systematically progress from foundational packaging principles to high-density substrates and interposers, vertical 3D integration, and the fastest-evolving fan-out wafer/panel technologies. The course culminates in an analysis of the bleeding edge of semiconductor engineering: hybrid bonding, next-generation glass core substrates, and competing high-density architectures (such as TSMC’s CoWoS and Intel’s Foveros).
For workshop details, pls refer to the link
https://docs.google.com/document/d/1HykElhnj--A_i7VYsMcsu9n0SflFkTOw9trRKe4sraY/edit?tab=t.0
System-in-Package (SiP) Technology: Materials, Packaging Processes, and Thermal-Electrical Performance (25-26 Feb 2027)
As consumer demand shifts toward smarter, more compact, and multi-functional electronic products, advanced integrated circuit (IC) packaging has evolved from a simple protective housing into a critical performance differentiator. System-in-Package (SiP) technology stands at the forefront of this revolution. It enables the integration of multiple chips and components into a single package to deliver unprecedented performance, power efficiency, and small-footprint solutions across the wireless, microprocessor, power, and automotive sectors.
This comprehensive, technical workshop is designed to bridge the gap between architectural concept, physics-of-failure design, and high-yield factory manufacturing. Over 5 structured modules, participants will master the entire SiP lifecycle: starting with strategic architecture trade-offs against System-on-Chip (SoC), advancing through critical electrical-thermal co-design, and diving deep into high-density interconnects, materials science of lead-free board assembly, and sequential front-to-back manufacturing process flows.
Power Electronics Packaging: Thermal Management, AMB Substrates, and Sintering (26 -27 Nov 2026)
This comprehensive workshop provides an end-to-end deep dive into the power electronics packaging ecosystem, bridging the gap between semiconductor design, manufacturing hardware, and global supply chain dynamics. Participants will explore the foundational physics of thermal management—including conduction, convection, and radiation—before examining critical structural components like stamped/etched leadframes and high-performance ceramic substrates (HTCC, LTCC, and AMB). The curriculum details the evolution of discrete and power module packaging architectures, highlighting advanced methodologies such as copper clip technology, dual-side cooling, and embedded packaging designed to meet modern efficiency demands.
Beyond structural design, the technical agenda addresses cutting-edge material innovations—including silver/copper sintering, transient liquid phase sintering (TLPS), and advanced encapsulation—alongside a rigorous analysis of power device reliability and failure mechanisms like thermo-mechanical stress, electromigration, and corrosion. Crucially, the workshop contextualises these technical insights within the broader commercial landscape, analyzing the IDM-dominated wafer fabrication landscape, the OSAT ecosystem, and critical supply chain bottlenecks. Attendees will leave with a strategic understanding of emerging market trends, including regional diversification and the industry-wide shift toward advanced packaging solutions.
For workshop details, pls refer to the link
https://docs.google.com/document/d/1ntQolDRmNv71SviE3hVC6ZWdPBpF14P68LBQvmnFpaA/edit?tab=t.0
Interconnect Solutions for Advanced Packaging: Thermocompression, and Hybrid Bonding (11-12 Mar 2027)
As traditional Moore’s Law scaling approaches its physical limits, monolithic System-on-Chip (SoC) architectures face severe size and economic yield constraints. Concurrently, the exponential rise of artificial intelligence (AI), high-performance computing (HPC), and 5G/6G applications demands unprecedented interconnect density, superior power efficiency, and aggressive thermal management. Consequently, the frontier of semiconductor innovation has officially shifted from transistor scaling to heterogeneous integration and advanced packaging.
This intensive professional workshop provides an end-to-end technical deep dive into the critical interconnect technologies enabling next-generation silicon architectures. Bridging the gap between high-level architectural concepts and high-yield manufacturing reality, the curriculum guides participants from mainstream foundational methods up to leading-edge, sub-micron innovations. By mastering these packaging vectors, teams can successfully enable three-dimensional integrated circuits (3DICs), establishing a vital scaling pathway to sustain the growth and economic viability of Moore's Law. Technical leaders, engineers, and designers will gain the actionable insights required to successfully navigate the advanced packaging landscape and master the transition to sub-10 µm gapless integration.
For workshop details, pls refer to the link
https://docs.google.com/document/d/1pnbSqAIach540SMNRERh-5RqTPaNzopx_qGalbMsoJM/edit?tab=t.0
Wafer-Level Packaging: Engineering RDL, Bumping, and Reliable Flip Chip Interconnect (15-16 Apr 2027)
Bridging Silicon Layouts, Materials Rheology, and Thermo-Mechanical Reliability
The rapid scaling of High-Performance Computing (HPC), AI accelerators, and mobile chiplet architectures has shifted the primary performance bottleneck from the silicon transistor directly to the package interconnect. Modern high-density designs (chiplets, SiPs, and advanced accelerators) must successfully translate sub-micron silicon layout grids into macroscopic package dimensions. This vast geometric mismatch introduces severe spatial registration errors, intense thermo-mechanical stress, and complex interfacial metallurgical variations.
This advanced professional engineering workshop delivers deep, quantitative mastery over the physics, chemistry, and layout design rules governing modern wafer-level packaging (WLP) and flip chip technologies. Moving systematically from wafer-level lithography to downstream physical assembly, the curriculum provides a practical engineering framework to analyze material kinetics, interface metallurgy, and mechanical failure mechanisms.
For workshop details, pls refer to the link
https://docs.google.com/document/d/1nlU4m6zkbgpGZkb_owSazrcNPiCF_Y7UcruXJPiL40A/edit?tab=t.0
Breaking Down Panel level & Fan-out Wafer- Level Packaging: Design, Assembly, and its Competitive Technologies (10-11 May 2027)
As the semiconductor industry hits the economic and physical limits of monolithic SoC scaling, advanced packaging has emerged as the true engine of Moore’s Law. High reticle-size constraints and soaring mask costs at leading-edge nodes are forcing a paradigm shift toward modular silicon architectures. This intensive, commercial-grade technical workshop breaks down the engineering, manufacturing, and strategic design principles behind Fan-Out Wafer-Level Packaging (FO-WLP) and Panel-Level Packaging (PLP)—the foundational pillars of modern system scaling.
Engineers, architects, and product managers will discover how to achieve high-performance heterogeneous integration using high-productivity, TSV-less architectures. A primary focus of the workshop is the rise of 2.3D packaging alternatives, which utilize high-density organic or fine-pitch Redistribution Layers (RDL) to bypass the exorbitant cost and supply chain bottlenecks of traditional silicon interposers (2.5D). By evaluating these TSV-less alternatives, attendees will learn how to leverage existing manufacturing infrastructures (such as modified PCB or display panel lines) to significantly lower capital expenditure (CapEx) and overall Total Cost of Ownership (TCO).
For workshop details, pls refer to the link
https://docs.google.com/document/d/13eaRh8dpxG91zH4i_uZwh9ROs9efaWkA6xmFlBioj1k/edit?tab=t.0
For workshop details, pls refer to the link
https://docs.google.com/document/d/1fBSyBAmAurKQjwaB-PzRrvEhrMiFzzDCCiUe5v0WrLU/edit?tab=t.0
For workshop details, pls refer to the link
https://docs.google.com/document/d/1fBSyBAmAurKQjwaB-PzRrvEhrMiFzzDCCiUe5v0WrLU/edit?tab=t.0