join us in upcoming EVEntS
Upcoming Workshops (Singapore)
Workshops for learning
Chiplet & Heterogeneous Integration for Advanced Packaging
(8-9 Jan 2026)
This comprehensive program covers the evolution from traditional IC packaging to chiplet-based and heterogeneous integration architectures, highlighting the market trends and technology drivers shaping modern electronics. Participants will delve into IC carriers and substrates as the foundation of multi-chip integration, gain hands-on understanding of 3D packaging and TSV processes for vertical stacking, and examine cutting-edge fan-out and panel-level packaging solutions. The workshop concludes with an exploration of emerging technologies—including hybrid bonding, glass core substrates, and advanced substrate architectures (2.1D–3.5D)—that are redefining performance, scalability, and design flexibility in semiconductor systems.
Interconnect Solutions for Chiplet and Heterogeneous Integration: Flip Chip, Thermocompression, and Hybrid Bonding
(22-23 Jan 2026)
Advance your understanding of next-generation semiconductor packaging with this comprehensive workshop on interconnect technologies. Beginning with the fundamentals of packaging performance and reliability, the program explores mechanical, thermal, electrical, and chemical design factors, as well as heterogeneous integration architectures such as SoC, SiP, and chiplets. Participants will gain in-depth knowledge of key bonding technologies—including Flip Chip (C4 and thermocompression), Thermocompression Bonding for fine-pitch applications, and Hybrid Bonding for sub-10 µm interconnects. Through detailed process insights, design considerations, and material innovations, this workshop equips engineers with the technical expertise to enhance performance, yield, and scalability in advanced packaging systems.
For more details of the workshops, pls sent email to admin@launchxtec.com
Venue: Newcastle Australia Institute of Higher Education Singapore, 230 Victoria Street, #04-09/10, Bugis Junction Towers, S188024
Registration fee: SGD 800 per workshop (3 weeks before the workshop) and SGD 1,000 per workshop thereafter. We are pleased to offer the following discounts for block booking:
10% discount for registering for 3–5 workshops (any combination)
15% discount for registering for 6–8 workshops (any combination)
20% discount for registering for 9 or more workshops (any combination)
Please request a quotation by emailing admin@launchxtec or proceed with registration and payment via PayNow.
👉 Register now for Jan - Feb workshops through the link below to secure your spot:
Glass Core Substrates for Advanced Packaging: Materials, Processes, and Integration
(5-6 Feb 2026)
Discover how glass substrates are redefining the future of advanced semiconductor packaging in this comprehensive workshop. Learn why glass is emerging as a superior alternative to silicon and organic materials, offering unmatched dimensional stability, low dielectric loss, and high flatness. The program covers material and performance advantages, key design rules, and fabrication processes such as through-glass via (TGV) formation, metallization, and redistribution layers. Participants will explore diverse applications—from HPC and AI accelerators to RF and photonics—along with insights into reliability testing, manufacturing challenges, and the evolving global supply chain. The workshop concludes with a forward-looking view on research directions, scalability, and the role of glass substrates in next-generation 3D and chiplet-based integration.
System-in-Package Assembly for High-Performance and Heterogeneous Integration
(12 -13 Mar 2026)
This workshop delivers a comprehensive introduction to System-in-Package (SiP) technology, beginning with the role of IC packaging in enabling compact, high-performance, and application-driven electronic systems and comparing SiP and SoC approaches across wireless, computing, power, and automotive markets. Participants gain a solid foundation in thermal and electrical management, covering heat transfer, thermal modeling, signal integrity, EMI, and noise mechanisms critical to reliable high-speed designs, followed by detailed coverage of interconnect technologies, board-level assembly, and soldering with emphasis on Pb-free materials and reliability. The program concludes with an in-depth review of SiP assembly processes—from wafer thinning and die attach to encapsulation, plating, and trim-and-form—providing a holistic view of manufacturing flow and reliability considerations. This workshop is tailored to help engineers quickly get up to speed on the latest assembly technologies, materials, and industry best practices.
Wafer-Level Packaging and C4 Flip Chip Interconnects for Advanced Semiconductor Integration
(26-27 Mar)
This intensive two-day workshop delivers a detailed yet practical overview of C4 Flip Chip and Wafer-Level Packaging (WLP) technologies, with emphasis on the materials, process integration, and reliability challenges that enable high-density, high-performance semiconductor systems. Participants will explore heterogeneous integration trends, wafer-level interconnect fundamentals, and the evolution of Redistribution Layer (RDL) and Underbump Metallization (UBM) architectures that support fine-pitch C4 assemblies. The workshop covers wafer bumping and lead-free solder technologies, multiple bonding mechanisms including C4, thermocompression, and solid-state bonding, and critical design considerations for wafer-level integration. It concludes with in-depth discussion of characterization and reliability evaluation methods—such as interfacial analysis, failure mechanisms, temperature cycling, thermal shock, and moisture sensitivity—providing engineers with the knowledge to design, manufacture, and qualify reliable C4 flip chip and WLP solutions.
Breaking Down Panel level & Fan-out Wafer-Level Packaging: Design, Assembly, and Competitive Technologies
(23-24 Apr 2026)
This workshop provides a comprehensive overview of chiplet-based and heterogeneous integration technologies, starting with IC packaging fundamentals, key market and technology drivers, and the industry shift from monolithic SoC toward modular SiP and chiplet architectures to enable scalability, performance, and design flexibility. It introduces Wafer Level Packaging with a focus on the limitations of Fan-In WLP and the advantages, evolution, and industry adoption of Fan-Out WLP as a critical enabler for high-density integration. Participants then explore wafer-level and panel-level FO-WLP through die-first and die-last architectures, real-world case studies from leading vendors, key assembly and reliability challenges, and future scaling toward PoP and panel-level manufacturing. The workshop concludes with an examination of emerging and competing technologies for advanced chiplet systems, including next-generation substrates, multi-dimensional packaging concepts, hybrid bonding, and glass core substrates, offering a forward-looking perspective on the future of advanced semiconductor packaging.
👉 Register now for Mar - Apr through the link below to secure your spot:
