join us in upcoming EVEntS
Upcoming Workshops (Singapore)
Workshops for learning
For more details of the workshops, pls sent email to admin@launchxtec.com
Venue: Newcastle Australia Institute of Higher Education Singapore, 230 Victoria Street, #04-09/10, Bugis Junction Towers, S188024
Registration fee: SGD 800 per workshop (3 weeks before the workshop) and SGD 1,000 per workshop thereafter. We are pleased to offer the following discounts for block booking:
10% discount for registering for 3–5 workshops (any combination)
15% discount for registering for >6 workshops (any combination)
Please request a quotation by emailing admin@launchxtec.com or proceed with registration and payment via PayNow.
Next-Generation 3D Packaging: 3DIC integration and TSV Technology
(20-21 Aug)
This specialized program delivers a rigorous technical deep dive into the architectures, fabrication flows, and real-world deployment of 3D Integrated Circuits (3D ICs) and Through-Silicon Vias (TSVs). Attendees will master the transition from monolithic SoC design to modern multi-dimensional scaling, analyzing the structural differences, benefits, and challenges of 3D, 3.5D, and 4D packaging. By examining advanced platforms like TSMC’s SoIC alongside Wafer-to-Wafer (W2W) and Die-to-Wafer (D2W) bonding paradigms, you will gain a functional blueprint for implementing high-density silicon architectures tailored for high-performance computing, AI hardware, and next-generation memory systems.
The curriculum provides an exhaustive, step-by-step breakdown of the TSV lifecycle, exploring processing variations across Via-First, Via-Middle, and Via-Last configurations alongside critical Keep-Out Zone (KOZ) design rules. Participants will evaluate high-precision fabrication processes, comparing Deep Reactive-Ion Etching (DRIE) with laser methods, and analyzing thin-film deposition (SACVD, PECVD, ALD), barrier/seed layer formation, and bottom-up super-conformal copper plating. Finally, the workshop addresses critical back-end vulnerabilities by teaching techniques to mitigate thermal hotspot stresses, eliminate electrical voids, and apply advanced Failure Analysis (FA) to maximize production yield and package reliability.
For workshop details, pls refer to the link
https://docs.google.com/document/d/1AbYJKKeZZu98-N7FPbAXML7fViukWy7JgMLV-0ytzFE/edit?usp=sharing
Package Reliability Management: Failure Mechanisms, Failure Analysis and Material Characterization Techniques
(17-18 Sep)
Ensure maximum semiconductor uptime and seamless qualification with our comprehensive Package Reliability Management & Failure Mechanisms Workshop. This intensive masterclass bridges the gap between material science and product longevity by providing actionable strategies to implement rigorous Design for Reliability (DFR) principles. Participants will master global compliance frameworks, including JEDEC and IEC standards, while developing a deep predictive understanding of cross-disciplinary failure modes. From evaluating thermo-mechanical stresses and physical delamination to diagnosing chemical corrosion and electrical electromigration, this module equips engineering teams with the analytical foresight needed to mitigate risks before they impact the production line.
Complementing risk management, the curriculum delivers a robust framework for physical isolation and diagnostic precision through advanced Failure Analysis (FA) and Material Characterization workflows. Attendees will gain direct insight into non-destructive testing methodologies like Scanning Acoustic Microscopy (SAM) and high-resolution imaging using SEM, EDX, and Focused Ion Beam (FIB) milling. Additionally, the program demystifies bulk thermal behaviors and interface integrity, instructing participants on how to evaluate adhesion via wire-pull and die-shear testing alongside advanced characterization tools like TGA, DSC, and DMA. Secure your asset lifecycle assurance—register today to turn complex package vulnerabilities into predictable, yield-improving outcomes.
For workshop details, pls refer to the link
https://docs.google.com/document/d/18LmxC6FPL4D3TG1PxfbVemL6ThRQohRT_8lTsdwtaLU/edit?usp=sharing
Insight to Co-packaged Optics: Hetergoeneous Integration with 3D packaging
(22-23 Oct)
This advanced technical workshop provides an exhaustive, end-to-end deep dive into Co-Packaged Optics (CPO), tracing its evolution from legacy pluggable transceivers to the heterogeneous integration of optical engines directly onto the ASIC substrate. Designed for packaging engineers, semiconductor designers, and network architects, the curriculum systematically breaks down the physics of 112G/224G SerDes drivers, multi-die silicon co-design (ASIC, PIC, and EIC), and the micro-architectural differences between 2D, 2.3D, 2.5D (CoWoS/EMIB), and 3D hybrid bonding configurations. Participants will analyze material trade-offs across organic, silicon, and glass substrates while mastering the deployment of high-density interposers, TSVs, and substrate cavities necessary to sustain extreme I/O densities.
Beyond structural architecture, the workshop confronts critical physical and manufacturing bottlenecks, focusing on advanced thermal management strategies to mitigate CTE mismatch and severe hotspot gradients using micro-channel liquid cooling. The technical progression covers wafer-to-wafer (W2W) and die-to-wafer (D2W) assembly flows, sub-micron passive/active optical alignment techniques, and rigorous reliability testing under mechanical and environmental stress. Ultimately, attendees will gain actionable engineering frameworks to design, assemble, and scale high-performance CPO systems, positioning them at the forefront of next-generation switching fabrics, AI/GPU compute clusters, and optically disaggregated memory architectures.
For workshop details, pls refer to the link
https://docs.google.com/document/d/1GGOIRQEC1DEXopHFZ6TO2cmRgnvc5MmYto9tfZBP3Jo/edit?usp=sharing