join us in upcoming EVEntS
Upcoming Workshops (Singapore)
Workshops for learning
For more details of the workshops, pls sent email to admin@launchxtec.com
Venue: Newcastle Australia Institute of Higher Education Singapore, 230 Victoria Street, #04-09/10, Bugis Junction Towers, S188024
Registration fee: SGD 800 per workshop (3 weeks before the workshop) and SGD 1,000 per workshop thereafter. We are pleased to offer the following discounts for block booking:
10% discount for registering for 3–5 workshops (any combination)
15% discount for registering for >6 workshops (any combination)
Please request a quotation by emailing admin@launchxtec.com or proceed with registration and payment via PayNow.
Power Electronics Packaging: Thermal Management, AMB Substrates, and Sintering
(26 -27 Nov)
Master the entire power electronics packaging and supply chain landscape in our upcoming intensive workshop. Designed for industry professionals, this comprehensive program bridges the gap between foundational power device architectures, wafer fabrication dynamics, and the shifting IDM-and-OSAT ecosystem. Participants will gain critical, actionable insights into current supply chain bottlenecks, risk mitigation strategies, and the accelerating regional diversification driving the industry toward advanced packaging technologies.
Moving from macro supply chain dynamics to core engineering fundamentals, the technical sessions will dive deep into thermal management, leadframe manufacturing, and substrate innovations. You will explore thermal fundamentals alongside high-performance materials like Active Metal Brazing (AMB) substrates, and compare discrete versus power module packaging approaches—including copper clips, silver/sintering adoption, and dual-side cooling. Secure your spot today to navigate the technical challenges and market trends shaping the future of power packaging.
Insight to Co-packaged Optics: Heterogeneous Integration with 3D packaging
(22-23 Oct)
This advanced technical workshop provides an exhaustive, end-to-end deep dive into Co-Packaged Optics (CPO), tracing its evolution from legacy pluggable transceivers to the heterogeneous integration of optical engines directly onto the ASIC substrate. Designed for packaging engineers, semiconductor designers, and network architects, the curriculum systematically breaks down the physics of SerDes drivers, multi-die silicon co-design (ASIC, PIC, and EIC), and the micro-architectural differences between 2D, 2.3D, 2.5D (CoWoS/EMIB), and 3D hybrid bonding configurations. Participants will analyze material trade-offs across organic, silicon, and glass substrates while mastering the deployment of high-density interposers, TSVs, and substrate cavities necessary to sustain extreme I/O densities.
Beyond structural architecture, the workshop confronts critical physical and manufacturing bottlenecks, focusing on advanced thermal management strategies to mitigate CTE mismatch and severe hotspot gradients using micro-channel liquid cooling. The technical progression covers wafer-to-wafer (W2W) and die-to-wafer (D2W) assembly flows, sub-micron passive/active optical alignment techniques, and rigorous reliability testing under mechanical and environmental stress. Ultimately, attendees will gain actionable engineering frameworks to design, assemble, and scale high-performance CPO systems, positioning them at the forefront of next-generation switching fabrics, AI/GPU compute clusters, and optically disaggregated memory architectures.
For workshop details, pls refer to the link
https://docs.google.com/document/d/17CY_Emj1fd454CRPfGfhbZ5t9x6UiV8StbRbs5sSIAM/edit?usp=sharing
For workshop details, pls refer to the link
https://docs.google.com/document/d/1fBSyBAmAurKQjwaB-PzRrvEhrMiFzzDCCiUe5v0WrLU/edit?usp=sharing